1. Field of the Invention
The present invention relates to a semiconductor device having a memory cell which is made up of one FG (Floating Gate) transistor and one selector gate transistor and, more particularly, to a potential applied to a well region where a source line or memory cell is formed, in order to read by decreasing the effective threshold voltage of a selector gate transistor in data read in, e.g., a nonvolatile semiconductor memory device.
2. Description of the Related Art
As one kind of logic-embedded semiconductor memory device of which relatively high-speed read is required, there is proposed a nonvolatile semiconductor memory device having a memory cell which is made up of an FG transistor (cell transistor) and selector gate transistor. A memory cell of this type is described in, e.g., T. Ditewing et al., “An Embedded 1.2V-Read Flash Memory Module in a 0.18 μm Logic Process”, 2001 IEEE ISSCC Digest 2.4, pp. 34-35, February/2001. In a memory cell described in this reference, the drain of an FG transistor is connected to a bit line, its source is connected to the drain of a selector gate transistor, and the source of the selector gate transistor is connected to a source line. A signal output from a word line driver is supplied to the control gate of the FG transistor and the gate of the selector gate transistor to drive these transistors.
As a nonvolatile semiconductor memory device having a similar memory cell structure, there is known a NAND flash memory disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. H07-073688. The memory cell of the NAND flash memory is made up of a plurality of FG transistors and two selector gate transistors. The current paths of the FG transistors are series-connected, and the selector gate transistors are respectively interposed between the bit line and the drain side of the series-connected FG transistors and between the source line and their source side.
Since no selector gate transistor exists on the drain side in the memory cell described in the above reference, the memory cell is not influenced by the channel resistance of the selector gate transistor on the drain side in read. Hence, the cell current can be set large to perform read quickly.
On the other hand, a potential applied to an unselected bit line in write must be stopped in the selector gate transistor on the source side so as not to supply any current from the unselected bit line to the source line. For this reason, a stricter leakage current characteristic is required of the selector gate transistor than a NAND transistor.
The leakage current of the selector gate transistor in write and the read speed of the memory cell have a tradeoff relationship because of the following reasons.
A conventional read method is executed by procedures (1) to (3).
(1) A bit line BL is precharged to, e.g., 0.9 V while 0 V is applied to all of a control gate CG of an FG transistor, a gate SG of a selector gate transistor, and a source line SL.
(2) After that, the gate SG of the selector gate transistor is set to a power supply voltage Vcc. If data stored in the memory cell is “1” (=positive threshold voltage Vth), no current flows, and the bit line BL is kept at 0.9 V. If data in the memory cell is “0” (=negative threshold voltage Vth), a current flows, and the potential of the bit line BL gradually drops from 0.9 V.
(3) After a predetermined wait time (time taken to sufficiently decrease the potential of the bit line BL for data “0”), a sense amplifier is operated to read the potential of the bit line BL and finalize read data.
At this time, the following problems may occur.
More specifically, the wait time until the sense amplifier is operated in read is determined by a memory cell current. As the memory cell current is larger, the potential of the bit line BL drops more quickly, and the wait time can be shortened. In other words, a quick-read memory can be implemented.
For this purpose, it is desirable that the threshold voltage of the selector gate transistor is low enough not to adversely influence the read current by the channel resistance of the selector gate transistor. When the threshold voltage of the selector gate transistor is high, the read current of the memory cell becomes large.
In this manner, a low threshold voltage of the selector gate transistor results in a high read speed. However, an excessively low voltage cannot prevent (leaks) punch-through generated by a write inhibit potential which is applied to the bit line in write, and a write error may occur.
In write, a write inhibit voltage of, e.g., 7 V is applied to the bit line BL in a voltage application state in which 20 V is applied to the control gate CG of the FG transistor, 0 V is applied to the gate SG of the selector gate transistor, and 0 V is applied to the source line SL. Since the 7-V voltage is applied between the bit line BL and the source line SL, the threshold voltage of the selector gate transistor must be high enough to stop punch-through generated by the applied voltage.
In particular, a write error is fatal to a semiconductor memory device, and the threshold voltage of the selector gate transistor must be so set as not to generate any write error. For this purpose, the read speed of the memory cell must be sacrificed, and thus the leakage current and read speed have a tradeoff relationship.
As described above, in a conventional semiconductor device, it is difficult to suppress the leakage current of the selector gate transistor small while ensuring a satisfactory read speed of the memory cell.